The present disclosure relates to a duty ratio correction circuit adjusting a duty ratio of a signal, and to a phase synchronization circuit provided with such a duty ratio correction circuit.
In an electronic circuit, a clock signal is often used. Typically, a duty ratio of the clock signal may be desirably about 50%; however, for example, the duty ratio may deviated from about 50% due to characteristics of a buffer circuit, a load, or the like. In such a case, a duty ratio correction circuit correcting the duty ratio is often used.
Various technologies about such a duty ratio correction circuit have been disclosed. For example, in Japanese Unexamined Patent Application Publication No. H11-243327, a circuit that acquires a DC level of a clock signal with use of a low pass filter and performs negative feedback control of a rise time and a fall time of the clock signal so that the DC level becomes about half of a source voltage has been disclosed.